1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit device and a method of making the same, and more particularly to a Bi-MOS type semiconductor integrated circuit device which includes a bipolar transistor and an insulated gate transistor on a semiconductor substrate.
2. Description of the Related Art
FIG. 5 shows a cross-sectional view of a conventional Bi-MOS type semiconductor integrated circuit device (hereinafter abbreviated as Bi-MOS IC) having a bipolar transistor and an insulated gate transistor on a semiconductor substrate.
As shown in FIG. 5, a P-type epitaxial layer 14 is provided on a P.sup.- -type silicon substrate 10 having an N.sup.+ -type buried layer 12. An N-type impurity is diffused into the epitaxial layer 14 down to the buried layer 12 to provide island regions including N-type region 16 and 18, and the remaining P-type region 14. These island regions are electrically isolated by a field oxide film 22. The N-type region 18 serves as a collector region of two bipolar transistors and includes an N.sup.+ -type collector contact region 20. The P-type region 14 is a region for providing an insulated gate MOS transistor. The N-type region 16 is provided to form diodes, which includes P-type diffused regions 39. The P-type region 14 has N-type LDD regions 58 and N.sup.+ -type source/drain contact regions 60. The bipolar transistor includes a P.sup.+ -type outer base region 38 and a P-type inner base region 40 which includes an N.sup.+ -type emitter region 62. The emitter region 62 is provided with an emitter electrode 54 having a stacked structure composed of an N-type polysilicon layer and a molybdenum silicide layer. The collector contact region 20 includes a collector electrode 52 having the same stacked structure as the emitter electrode 54. Further, a gate electrode 56 having the same stacked structure as the emitter electrode 54 is provided by a gate oxide film 24 on the P-type region 14 located between the N-type LDD regions 58. The surface of the semiconductor substrate is covered with an interlevel insulator 64, in which contact holes reaching the above-mentioned regions are provided. Electrode wiring layers 72, 74, 76, 78, and 80 connected to desired regions are provided through the contact holes.
The Bi-MOS IC having the described structure has been used for various purposes. For example, it is used as an amplifier circuit or a mixer circuit in VHF and UHF bands. For increasing high-frequency characteristics of the Bi-MOS IC, it is desirable to reduce the emitter-base capacitance of the bipolar transistor and the base resistance, thereby increasing the gain-bandwidth product f.sub.T. For this purpose, it is necessary to provide the fine pattern structure of the bipolar transistor, more specifically, to reduce the emitter pitch Lp.
However, it is difficult to reduce the emitter pitch Lp in the conventional Bi-MOS IC, because of the following reason.
FIG. 6 shows a method of making the conventional Bi-MOS IC. Contact holes 100 are formed in an insulating film 34 provided on the collector region 18, so as to reach the collector contact region 20 and the inner base region 40. Collector electrodes 52, emitter electrodes 54 and the gate electrode 56, which are composed of the doped polysilicon layer and the metal silicide, are provided on respective regions through the contact holes. Thereafter, the interlevel insulator 64 is formed on the collector region 18 as shown in FIG. 7. Contact holes 102 are formed in the interlevel insulator 64 so as to reach the outer base regions 38, the emitter electrodes 54, and the collector electrodes 52.
As described above, since the contact holes 100 for providing the emitter electrodes and the contact holes 102 for obtaining the base electrodes are formed by different process steps, a mask alignment margin and an etching margin must be taken into account. Therefore, it is difficult to reduce the emitter pitch Lp, thereby reducing the emitter-base capacitance and the base resistance, in order to improve the gain-bandwidth product f.sub.T.